欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM6A9320BIA 参数 Datasheet PDF下载

EM6A9320BIA图片预览
型号: EM6A9320BIA
PDF下载: 下载PDF文件 查看货源
内容描述: 4M ×32位DDR同步DRAM (SDRAM)的 [4M x 32 bit DDR Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 52 页 / 446 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
 浏览型号EM6A9320BIA的Datasheet PDF文件第9页浏览型号EM6A9320BIA的Datasheet PDF文件第10页浏览型号EM6A9320BIA的Datasheet PDF文件第11页浏览型号EM6A9320BIA的Datasheet PDF文件第12页浏览型号EM6A9320BIA的Datasheet PDF文件第14页浏览型号EM6A9320BIA的Datasheet PDF文件第15页浏览型号EM6A9320BIA的Datasheet PDF文件第16页浏览型号EM6A9320BIA的Datasheet PDF文件第17页  
EM6A9320BIA  
EtronTech  
Table 18. Electrical Characteristics and Recommended A.C. Operating Conditions  
(VDD = 2.5V ± 5%, TA = 0~70 °C)  
-4  
-5  
Symbol  
Parameter  
Unit  
Min.  
4
Max.  
10  
Min.  
5
Max.  
10  
tCK  
tCH  
tCL  
Clock cycle time  
CL = 3  
ns  
tCK  
tCK  
Clock high level width  
Clock low level width  
0.45  
0.45  
0.55  
0.55  
0.45  
0.45  
0.55  
0.55  
tDQSCK DQS-out access time from CK,  
-0.7  
-0.7  
0.7  
0.7  
-0.7  
-0.7  
0.7  
0.7  
ns  
ns  
CK  
tAC  
Output access time from CK,  
CK  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
DQS-DQ Skew  
Read preamble  
Read postamble  
CK to valid DQS-in  
-
0.4  
-
0.4  
ns  
tCK  
tCK  
tCK  
ns  
0.9  
0.4  
0.85  
0
1.1  
0.9  
0.4  
0.8  
0
1.1  
0.6  
0.6  
1.15  
1.2  
tWPRES DQS-in setup time  
tWPRE DQS Write preamble  
-
-
0.35  
0.4  
0.4  
0.4  
0.9  
0.9  
0.45  
0.45  
-
0.25  
0.4  
0.4  
0.4  
1.0  
1.0  
0.45  
0.45  
-
tCK  
tCK  
tCK  
tCK  
ns  
tWPST  
tDQSH  
tDQSL  
tIS  
DQS write postamble  
0.6  
0.6  
DQS in high level pulse width  
DQS in low level pulse width  
-
-
-
-
-
-
-
-
-
-
-
-
Address and Control input setup time  
Address and Control input hold time  
DQ & DM setup time to DQS  
tIH  
ns  
tDS  
ns  
tDH  
DQ & DM hold time to DQS  
ns  
t
CLMIN or  
tCHMIN  
t
CLMIN or  
tCHMIN  
tHP  
Clock half period  
-
-
ns  
tQH  
DQ/DQS output hold time from DQS  
Row cycle time  
tHP - tQHS  
-
tHP - tQHS  
-
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
µs  
ns  
ns  
tRC  
60  
68  
40  
20  
16  
3
-
60  
-
tRFC  
tRAS  
tRCD  
tRP  
Refresh row cycle time  
Row active time  
-
70  
-
100K  
40  
100K  
Active to Read or Write delay  
Row precharge time  
-
20  
-
-
18  
-
tRRD  
tWR  
Row active to Row active delay  
Write recovery time  
-
2
3
-
3
-
-
tMRD  
tDAL  
tXSRD  
tPDEX  
tREFI  
tIPW  
tDIPW  
Mode register set cycle time  
2
-
2
-
Auto precharge write recovery + Precharge time tWR + tRP  
-
tWR + tRP  
200  
tCK + tIS  
-
-
Self refresh exit to read command delay  
Power down exit time  
200  
tCK + tIS  
-
-
-
-
-
Refresh interval time  
7.8  
-
7.8  
-
Cntrol and Address input pulse width  
DQ & DM input pulse width (for each input)  
2.2  
2.2  
1.75  
-
1.75  
-
tHZ  
tLZ  
Data-out high-impedance window from CK/  
-
0.7  
0.7  
-
0.7  
0.7  
ns  
ns  
CK  
Data-out low-impedance window from CK/  
-0.7  
-0.7  
CK  
tQHS  
DVW  
Data Hold Skew Factor  
-
0.45  
-
0.5  
ns  
ns  
ns  
tCK  
Output data valid window  
tQH - tDQSQ  
-
-
-
tQH - tDQSQ  
-
-
-
tXSNR  
tCCD  
Exit Self-Refresh to non-Read command  
CAS# to CAS# Delay time  
75  
1
75  
1
Etron Confidential  
13  
Rev 1.7  
Nov. 2009