Et r on Tech
EM6A9325
4M x 32 LPSDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 2.3V~2.7V, Ta = -25~85°C) (Note: 1, 2, 3, 4)
-
75/8/1H/1L
Symbol
A.C. Parameter
Unit
Note
Min.
Max.
tRC
tRCD
tRP
Row cycle time( same bank )
65/66/70/84
20/20/20/24
20/20/20/24
5
5
RAS# to CAS# delay (same bank)
Precharge to refresh / row activate command
(same bank)
5
5
ns
ns
tRRD
Row activate to row active delay
(different banks)
15/16/20/20
45/46/50/60
tRAS
Row activate to percharge time
(same bank)
100,000
5
5
tRDL
tCK1
tCK2
tCK3
Last data in to row precharge
10
Clock cycle time
CL* = 1
CL* = 2
CL* = 3
- /- /- /25
10/10/10/12
7.5/8/10/10
2.5/2.7/3/3
2.5/2.7/3/3
Clock high time
Clock low time
tCH
tCL
ns
6
5
tAC1
tAC2
tAC3
tCCD
tOH
tLZ
Access time from CLk
(positive edge)
CL* = 1
CL* = 2
CL* = 3
- /- / -/18
6/6/6/6
5.5/5.6/6/6
CAS# to CAS# Delay time
Data output hold time
1
2
1
CLK
ns
5
5
5
Data output low impedance
Data output high impedance
tHZ1
tHZ2
tHZ3
tIS
CL* = 1
CL* = 2
CL* = 3
-/- /-/18
6/6/6/6
4
5.5/5.6/6/6
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Refresh period (4096 refresh cycles)
2.5/2.7/3/3
1
6
6
tIH
ns
tREF
64
ms
*CL is CAS# Latency.
Preliminary
17
Rev 0.4
June 2003
ETRON [ ETRON TECHNOLOGY, INC. ]
