EM6A9325BG-8G 参数 Datasheet PDF下载

EtronTech

7

4M x 32 LPSDRAM

EM6A9325

Write and AutoPrecharge command (refer to the following figure)

(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after

the write operation. Once this command is given, any subsequent command can not occur within a

time delay of {(burst length -1) + t

WR

+ t

RP

(min.)}. At full-page burst, only the write operation is

performed in this command and the auto precharge function is ignored.

8

Mode Register Set command

(RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A11-A0 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The

Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst

Length in the Mode register to make SDRAM useful for a variety of different applications. The default

values of the Mode Register after power-up are undefined; therefore this command must be issued

at the power-up sequence. The state of pins BA0,1 and A11~A0 in the same cycle is the data written

to the mode register. One clock cycle is required to complete the write in the mode register (refer to

the following figure). The contents of the mode register can be changed using the same command

and the clock cycle requirements during operation as long as all banks are in the idle state.

T0

CLK

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

tCK2

CKE

Clock min.

CS#

RAS#

CAS#

WE#

Address Key

ADDR.

DQM

t

RP

DQ

Hi-Z

PrechargeAll

Mode Register

Set Command

Any

Command

Mode Register Set Cycle (CAS# Latency = 2, 3)

Preliminary

11

Rev 0.4

June 2003