EtronTech
Features
•
Fast clock rate: 250/200/166 MHz
•
Differential Clock CK & CK# input
4Mx32 DDR SDRAM
EM6A9320BI
4M x 32 DDR SDRAM
(Rev 0.9C May/2006)
Overview
The EM6A9320 DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 128
Mbits. It is internally configured as a quad 1M x 32
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and CK#.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence.
Accesses begin with the registration of a BankActivate
command, which is then followed by a Read or Write
command.
The EM6A9320 provides programmable Read or Write
burst lengths of 2, 4, 8 and full page. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
The refresh functions, either Auto or Self Refresh are
easy to use.
In addition, EM6A9320 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications requiring
high memory bandwidth, result in a device particularly
well suited to high performance main memory and
graphics applications.
•
4 Bi-directional DQS. Data transactions on both
edges of DQS (1DQS / Byte)
•
DLL aligns DQ and DQS transitions
•
Edge aligned data & DQS output
•
Center aligned data & DQS input
•
4 internal banks, 1M x 32-bit for each bank
•
Programmable mode and extended mode
registers
- CAS Latency: 2, 2.5, 3, 4
- Burst length: 2, 4, 8, and Full Page
- Burst Type: Sequential & Interleave
•
Full page burst length for sequential type only
•
Start address of full page burst should be even
•
All inputs except DQ’s & DM are at the positive
edge of the system clock
•
No Write-Interrupted by Read function
•
4 individual DM control for write masking only
•
Auto Refresh and Self Refresh
•
4096 refresh cycles / 32ms
•
Power supplies :
V
DD
= 2.5V
±
5%
V
DDQ
= 2.5V
±
5%
•
Interface : SSTL_2 I/O compatible
•
Standard 144-ball FBGA package
•
Pb-free package is availiable
Ordering Information
Part Number
EM6A9320BI-4M
EM6A9320BI-4MG
EM6A9320BI-5M
EM6A9320BI-5MG
EM6A9320BI-6M
EM6A9320BI-6MG
G : indicates Pb Free package.
Frequency
250MHz
250MHz
200MHz
200MHz
166MHz
166MHz
Power Supply Package
FBGA
FBGA
V
DD
2.5V
FBGA
V
DDQ
2.5V
FBGA
FBGA
FBGA