EtronTech
(VDD = 2.5V
±
5%, Ta = 0~70
°C)
Symbol
Parameter
4Mx32 DDR SDRAM
EM6A9320BI
5
6
Max
Min
Max
Unit
Electrical Characteristics and Recommended A.C. Operating Conditions
4
Min
Max
Min
t
CK
t
CH
t
CL
t
DQSCK
t
AC
t
DQSQ
t
RPRE
t
RPST
t
DQSS
t
WPRES
t
WPREH
t
WPST
t
DQSH
t
DQSL
t
IS
t
IH
t
DS
t
DH
t
HP
t
QHS
t
QH
t
RC
t
RFC
t
RAS
t
RCDRD
t
RCDWR
t
RP
t
RRD
tw
R
t
CDLR
t
CCD
t
MRD
t
DAL
t
XSA
t
PDEX
t
REF
t
J
t
R,
t
F
Clock cycle time
Clock high level width
Clock low level width
CL = 2
CL = 2.5
CL = 3
-
-
4
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.45
0.45
tCLMIN or
tCHMIN
-
-
-
10
0.55
0.55
0.7
0.7
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
75
6
5
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.25
0.4
0.4
0.4
1.0
1.0
0.5
0.5
tCLMIN or
tCHMIN
-
10
10
10
0.55
0.55
0.7
0.7
0.4
1.1
0.6
1.2
-
-
0.6
0.6
0.6
-
-
-
-
-
75
6
6
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.75
0
0.25
0.4
0.4
0.4
1.0
1.0
0.5
0.5
tCLMIN or
tCHMIN
12
12
12
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.25
-
-
0.6
0.6
0.6
-
-
-
-
-
ns
t
CK
t
CK
ns
ns
ns
t
CK
t
CK
t
CK
ns
tck
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
ns
us
ps
ps
DQS-out access time from CK,CK#
Output access time from CK,CK#
DQS-DQ Skew
Read preamble
Read postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS write postamble
DQS in high level pulse width
DQS in low level pulse width
Address and Control input setup time
Address and Control input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Clock half period
Data hold skew factor
Output DQS valid window
Row cycle time
Refresh row cycle time
Row active time
RAS# to CAS# Delay in Read
RAS# to CAS# Delay in Write
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. Address to Col. Address delay
Mode register set cycle time
Auto precharge write recovery + Precharge
Self refresh exit to read command delay
0.45
-
-
0.5
-
-
0.55
tHP -
t
QHS
10
tHP -
t
QHS
15
17
10
5
3
4
3
3
2
1
2
7
200
tIS + 2tCK
tHP -
t
QHS
12
14
8
4
2
4
2
2
2
1
2
6
200
tIS + 2tCK
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
100
700
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
105
700
12
7
3
2
3
2
2
2
1
2
6
200
tIS + 2tCK
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
105
700
Power down exit time
Refresh interval time
Short term jitter
CLK Rise time, Fall time
-
-
-
-
-
-
-
-
-
12
Rev 0.9C
May 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
