EtronTech
Mode Register Set (MRS)
4Mx32 DDR SDRAM
EM6A9320
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2, A1, A0)
•
This field specifies the data length of column access and selects the Burst Length.
Addressing Mode Select Field (A3)
•
The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and
Interleave Mode support burst length of 2, 4 and 8. Full page burst length is only for Sequential mode.
CAS# Latency Field (A6, A5, A4)
•
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS# Latency depends on the frequency of CK. The
minimum whole value satisfying the following formula must be programmed into this field.
CAS# Latency X t
CK
t
CAC
(min)
Test Mode field :A7; DLL Reset Mode field : A8
•
These two bits must be programmed to "00" in normal operation.
( BA0, BA1)
•
Mode Resistor Bitmap
BA1
0
BA0
A11
A10
A9
Mode RFU must be set to “0”
BA0
0
1
Register Mode
MRS
EMRS
A8
DLL
A8
0
1
0
A7
TM
A7
0
0
1
A6
A5
A4
CAS Latency
A3
BT
A3
0
1
A2
A1
A0
Burst Lenght
A6
0
0
1
1
A5
1
1
0
0
A4
CAS Latency
0
Reserved
1
3 clocks
0
4 clocks
1
5 clocks
All other Reserved
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Burst Length
2
4
Start Address
A2
A1
A0
X
X
0
X
X
1
X
0
0
X
0
1
X
1
0
X
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Sequential
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
Interleave
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
≦
Mode
Normal
Reset DLL
Test Mode
Type
Sequential
Interleave
A2
0
0
0
1
A1
0
1
1
1
A0
Burst Length
1
2
0
4
1
8
1
Full Page (Sequential)
All other Reserved
6
Rev 0.6
May. 2006