EtronTech
EM6A9160
8Mx16 DDR SDRAM
Electrical AC Characteristics (V
= 2.5 5%, Ta = 0~70 C)
±
°
DD
3.3
3.6
4.0
5.0
Symbol
Parameter
Clock cycle time
Unit
Min
-
Max
-
Min
3.6
-
Max
10
Min
Max
10
Min
5
Max
10
CL = 3
CL = 4
4
-
tCK
ns
3.3
0.45
10
-
-
-
-
Clock high level width
Clock low level width
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCH
tCL
tDQSCK
tAC
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
0.45
-0.6
-0.6
-
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
0.45
-0.6
-0.6
-
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
0.45
-0.6
-0.6
-
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
0.45
-0.7
-0.7
-
0.55
0.7
0.7
0.45
1.1
0.6
1.15
-
DQS-out access time from CK,CK#
Output access time from CK,CK#
DQS-DQ Skew
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
Read preamble
0.9
0.4
0.85
0
0.9
0.4
0.85
0
0.9
0.4
0.85
0
0.9
0.4
0.85
0
Read postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
-
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
-
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
-
0.3
0.4
0.4
0.4
1.0
1.0
0.45
0.45
-
DQS write postamble
0.6
0.6
0.6
-
0.6
0.6
0.6
-
0.6
0.6
0.6
-
0.6
0.6
0.6
-
DQS in high level pulse width
DQS in low level pulse width
Address and Control input setup time
Address and Control input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
-
-
-
-
tIH
tDS
tDH
ns
ns
ns
-
-
-
-
-
-
-
-
tCLMIN
or
tCHMIN
tCLMIN
or
tCHMIN
tCLMIN
or
tCHMIN
tCLMIN
or
tCHMIN
Clock half period
-
-
-
-
tHP
ns
tHP -
0.35
tHP -
0.4
tHP -
0.4
tHP -
0.45
Output DQS valid window
-
-
-
-
tQH
ns
Row cycle time
15
-
15
-
13
-
12
-
tRC
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
Refresh row cycle time
17
-
17
-
15
-
14
-
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
twR
tCDLR
tCCD
tMRD
tDAL
Row active time
10
100K
10
100K
9
100K
8
100K
RAS# to CAS# Delay in Read
RAS# to CAS# Delay in Write
Row precharge time
5
-
5
-
4
-
4
-
3
-
3
-
2
-
2
-
5
-
5
-
4
-
4
-
Row active to Row active delay
Write recovery time
3
-
3
-
3
-
3
-
3
-
3
-
3
-
3
-
Last data in to Read command
Col. Address to Col. Address delay
Mode register set cycle time
Auto precharge write recovery + Precharge
Self refresh exit to read command delay
Power down exit time
3
-
2
-
2
-
2
-
1
-
1
-
1
2
-
1
-
2
-
2
-
-
-
2
-
8
200
-
-
8
200
-
-
7
7
200
-
-
200
tCK + tIS
-
tXSA
tPDEX
tREF
tCK + tIS
-
-
tCK + tIS
-
-
-
tCK + tIS
-
-
Refresh interval time
7.8
7.8
7.8
7.8
us
13
Rev. 1.4
May 2006