EtronTech
EM6A9160
8Mx16 DDR SDRAM
Recommended A.C. Operating Conditions (V
= 2.5 5%, Ta = 0~70 C)
±
°
DD
Parameter
Input High Voltage (DC)
Input Low Voltage (DC)
Symbol
VIH (AC)
VIL (AC)
VID (AC)
Min.
Max.
Unit
V
Note
VREF + 0.35
VREF – 0.35
VDDQ + 0.6
V
Input Different Voltage, CLK and CLK#
inputs
0.7
V
Input Crossing Point Voltage, CLK and
CLK# inputs
VIX (AC)
0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. Power-up sequence is described in Note 6.
5. A.C. Test Conditions
SSTL_2 Interface
Reference Level of Output Signals (VRFE
)
0.5 * VDDQ
Reference to the Under Output Load (A)
VREF+0.35 V / VREF-0.35 V
1 V/ns
Output Load
Input Signal Levels
Input Signals Slew Rate
Reference Level of Input Signals
0.5 * VDDQ
0.5*VDDQ
25Ω
25Ω
Output
30pF
SSTL_2 A.C. Test Load
Power up Sequence
6.
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and maintain CKE “LOW”. Power applied to VDDQ the same time as VTT and VREF.
14
Rev. 1.4
May 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
