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EM6A9160TSC-5G 参数 Datasheet PDF下载

EM6A9160TSC-5G图片预览
型号: EM6A9160TSC-5G
PDF下载: 下载PDF文件 查看货源
内容描述: [8M x 16 DDR Synchronous DRAM]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 65 页 / 535 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM6A9160  
EtronTech  
Table 15. D.C. Characteristics  
(VDD = 2.5V±0.2V, TA = 0~70 °C)  
-4  
-5  
Parameter & Test Condition  
Symbol  
Unit  
Max.  
OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC (min);  
tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle;  
Address and control inputs changing once every two clock cycles.  
IDD0  
60  
55  
mA  
OPERATING CURRENT : One bank; Active-Read-Precharge; BL=4;  
tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing IDD1  
once per clock cycle  
75  
5
65  
5
mA  
mA  
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;  
IDD2P  
power-down mode; tCK=tCK(min); CKE=LOW  
IDLE STANDLY CURRENT : CKE = HIGH;  
banks idle; tCK=tCK(min); Address and control inputs changing once per  
clock cycle; VIN=VREF for DQ, DQS and DM  
=HIGH(DESELECT); All  
CS  
IDD2N  
IDD3P  
IDD3N  
30  
17  
40  
30  
17  
40  
mA  
mA  
mA  
ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-  
down mode; CKE=LOW; tCK=tCK(min)  
ACTIVE STANDBY CURRENT :  
=HIGH;CKE=HIGH; one bank active ;  
CS  
tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per  
clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle  
OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst;  
one bank active; Address and control inputs changing once per clock cycle; IDD4R  
tCK=tCK(min); lout=0mA;50% of data changing on every transfer  
120  
120  
100  
100  
mA  
mA  
OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous  
Burst ;one bank active; address and control inputs changing once per clock  
cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50%  
IDD4W  
of data changing on every transfer  
AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min)  
IDD5  
80  
2
70  
2
mA  
mA  
SELF REFRESH CURRENT: Self Refresh Mode ; CKE 0.2V;tCK=tCK(min) IDD6  
BURST OPERATING CURRENT 4 bank operation:  
Four bank interleaving READs; BL=4; with Auto Precharge; tRC=tRC(min);  
IDD7  
160  
140  
mA  
tCK=tCK(min); Address and control inputs change only during Active,  
READ , or WRITE command  
Figure 3: Timing Waveform for IDD7 Measurement at 200 MHz CK Operation  
CK  
CK  
tRCD  
READ  
AP  
READ  
AP  
READ  
AP  
READ  
AP  
ACT  
ACT  
ACT  
ACT  
ACT  
COMMAND  
ADDRESS  
...pattern repeats...  
Bank 1  
Row e  
Bank 0  
Row d  
Bank 3  
Col c  
Bank 0  
Col d  
Bank 2  
Row f  
Bank 1  
Col e  
Bank 3  
Row g  
Bank 2  
Col f  
Bank 0  
Row h  
CL=3  
DQS  
DQ  
D0 a  
D0 a D0 a D0 b  
D0 a  
D0 b D0 b D0 b  
D0 d D0 d  
D0 e  
D0 e  
D0 f  
D0 f  
D0 c D0 c D0 c D0 c  
D0 d D0 d D0 e  
D0 e  
11  
Rev. 1.3  
Apr. /2014