EtronTech
EM68C08CWAG
Figure 59. Asynchronous CKE LOW event
Stable clocks
tCK
CK#
CK
CKE
tDelay
tIS
CKE asynchronously drops LOW
Clocks can be turned off after this point
Figure 60. Clock frequency change in precharge power down mode
T0
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Ty+4
Tz
CK#
CK
DLL
RESET
CMD
CKE
ODT
NOP
NOP
NOP
NOP
NOP
Valid
Frequency Change Occurs here
200 Clocks
tIS
tIS
tXP
tRP
tAOFD
tIH
ODT is off during DLL RESET
Minimum 2 clocks required before
changing frequency
Stable new clock before power
down exit
Rev. 1.1
62
Apr. /2016