EtronTech
EM68C08CWAG
NOTE 9: tIS and tIH (input setup and hold) derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base)
and tIH(base) value to the ΔtIS and ΔtIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + ΔtIS
For slew rates in between the values listed in Tables 29, the derating values may obtained by linear interpolation.These
values are typically not subject to production test. They are verified by design and characterization.
Table 29. Derating values for DDR2-667, DDR2-800, DDR2-1066
△ tIS and △ tIH Derating Values for DDR2-667, DDR2-800, DDR2-1066
CK,CK# Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
△ tIS
△ tIH
△ tIS
△ tIH
△ tIS
△ tIH
Units
Notes
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+150
+143
+133
+120
+100
+67
0
-5
-13
-22
-34
+94
+89
+83
+75
+45
+21
0
-14
-31
-54
-83
-125
-188
-292
-375
-500
-708
-1125
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
-4
-30
-70
-138
-170
-295
-487
-970
+124
+119
+113
+105
+75
+51
+30
+16
-1
-24
-53
-95
-158
-262
-345
-470
-678
-1095
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+26
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Command/
Address Slew rate
(V/ns)
-23
-65
-60
0
-40
-100
-168
-200
-325
-517
-1000
-128
-232
-315
-440
-648
-1065
-108
-140
-265
-457
-940
NOTE 10: The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
NOTE 11: MIN (tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as
provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
NOTE 12: tQH = tHP – tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock HIGH or
clock LOW (tCH, tCL). tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel
to n-channel variation of the output drivers.
NOTE 13: tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the
output drivers as well as output slew rate mismatch between DQS / DQS# and associated DQ in any given
cycle.
NOTE 14: tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.WR refers to the tWR parameter stored in
the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer.
tCK refers to the application clock period.
NOTE 15: The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In
case of clock frequency change during precharge power-down.
NOTE 16: ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is
interpreted as 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual
input clock edges.
NOTE 17: ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when
the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin.
For DDR2-1066, if tCK(avg) = 1.875 ns is assumed, tAOFD is 0.9375 ns (= 0.5 x 1.875 ns) after the second
trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
Rev. 1.1
31
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
