EtronTech
EM68C08CWAE
Ball Descriptions
Table 3. Ball Descriptions
Symbol
Type
Description
CK, CK#
Input
Differential Clock: CK, CK# are driven by the system clock. All SDRAM input signals are
sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read)
data is referenced to the crossings of CK and CK# (both directions of crossing).
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
LOW synchronously with clock, the internal clock is suspended from the next clock cycle
and the state of output and burst address is frozen as long as the CKE remains LOW.
When all banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes.
BA0-BA2
A0-A13
Input
Input
Bank Address: BA0-BA2 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A13 are sampled during the BankActivate command (row address
A0-A13) and Read/Write command (column address A0-A9 with A10 defining Auto
Precharge). A13 Row Address use on x8 components only.
CS#
Input
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for
external bank selection on systems with multiple banks. It is considered part of the
command code.
RAS#
Row Address Strobe: The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the crossing of positive edges of CK
and negative edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is
asserted "HIGH" either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH" the BankActivate
command is selected and the bank designated by BA is turned on to the active state.
When the WE# is asserted "LOW" the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
CAS#
WE#
Input
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the crossing of positive
edges of CK and negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted
"LOW" the column access is started by asserting CAS# "LOW". Then, the Read or Write
command is selected by asserting WE# "HIGH" or "LOW".
Write Enable: The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the crossing of positive edges of CK and
negative edge of CK#. The WE# input is used to select the BankActivate or Precharge
command and Read or Write command.
DQS,
DQS#
Input /
Output
Bidirectional Data Strobe: output with read data, input with write data. Edge aligned
with read data, centered with write data. For the RDQS option using DM pin can be
enabled via the EMR(1) to simplify read timing.The data strobes DQS and RDQS may be
used in single ended mode or paired with the optional complementary signals DQS# and
RDQS# to provide differential pair signaling to the system during both reads and writes.
An EMRS (1) control bit enables or disables the complementary data strobe signals.
RDQS
RDQS#
DM
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
x8 device, the function of DM or RDQS/RQDS# is enabled by EMRS command.
DQ0 – DQ7 Input /
Output
Data I/O: Bi-directional data bus.
ODT
Input
On Die Termination: ODT enables internal termination resistance. It is applied to each
DQ, DQS/DQS#, RDQS/RDQS# and DM signal. The ODT pin is ignored if the EMR (1) is
programmed to disable ODT.
VDD
Supply
Power Supply: +1.8V ±0.1V
Rev. 1.3
5
Oct. /2015
ETRON [ ETRON TECHNOLOGY, INC. ]
