EtronTech
Functional Description
EM68B16CWPA
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and
continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an
Active command, which is then followed by a Read or Write command. The address bits registered coincident with
the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select
the row). The address bits registered coincident with the Read or Write command are used to select the starting
column location for the burst access and to determine if the auto precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command descriptions, and device operation.
Power-up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2*V
DDQ
and ODT
*1
at a low state (all other inputs may be
undefined.) The V
DD
voltage ramp time must be no greater than 200ms from when V
DD
ramps from 300mV to
V
DD
min; and during the V
DD
voltage ramp, |V
DD
-V
DDQ
| ≦ 0.3V
- V
DD
, V
DDL
and V
DDQ
are driven from a single power converter output, AND
- V
TT
is limited to 0.95 V max, AND
- V
REF
tracks V
DDQ
/2.
or
- Apply V
DD
before or at the same time as V
DDL
.
- Apply V
DDL
before or at the same time as V
DDQ
.
- Apply V
DDQ
before or at the same time as V
TT
& V
REF
.
At least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200µs after stable power and clock (CK, CK#), then apply NOP or deselect and take CKE
HIGH.
4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period.
5. Issue EMRS(2) command. (To issue EMRS (2) command, provide “LOW” to BA0, “HIGH” to BA1.)
6. Issue EMRS (3) command. (To issue EMRS (3) command, provide “HIGH” to BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "LOW" to A0, "HIGH" to BA0 and
"LOW" to BA1.)
8. Issue a Mode Register Set command for “DLL reset”.
(To issue DLL reset command, provide "HIGH" to A8 and "LOW" to BA0-1)
9. Issue precharge all command.
10. Issue 2 or more auto-refresh commands.
11. Issue a mode register set command with LOW to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).If OCD
calibration is not used, EMRS OCD Default command (A9=A8=A7=HIGH) followed by EMRS OCD calibration
Mo
de
Exit command (A9=A8=A7=LOW) must be issued with other operating parameters of EMRS.
13. The DDR2 SDRAM is now ready for normal operation.
NOTE 1:
To guarantee ODT off, V
REF
must be valid and a LOW level must be applied to the ODT pin.
Etron Confidential
8
Rev. 1.4
Mar. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
