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EM68A16CBQC-25H 参数 Datasheet PDF下载

EM68A16CBQC-25H图片预览
型号: EM68A16CBQC-25H
PDF下载: 下载PDF文件 查看货源
内容描述: [16M x 16 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 62 页 / 1022 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM68A16CBQC  
EtronTech  
Extended mode register for OCD impedance adjustment  
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven  
out by DDR2 SDRAM. In Drive (1) mode, all DQ, DQS signals are driven HIGH and all DQS# signals are driven  
LOW. In Drive (0) mode, all DQ, DQS signals are driven LOW and all DQS# signals are drive HIGH. In adjust mode,  
BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a  
nominal impedance value of 18 Ohms during nominal temperature and voltage conditions. Output driver  
characteristics for OCD calibration default are specified in the following table. OCD applies only to normal full  
strength output drive setting defined by EMRS and if half strength is set, OCD default driver characteristics are not  
applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable.  
After OCD calibration is completed or driver strength is set to default, subsequent EMRS commands not intended to  
adjust OCD characteristics must specify A7~A9 as ’000’ in order to maintain the default or calibrated value.  
Table 9. OCD drive mode program  
A9  
A8  
A7  
operation  
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD calibration mode exit  
Drive(1) DQ, DQS, HIGH and DQS# LOW  
Drive(0) DQ, DQS, LOW and DQS# HIGH  
Adjust mode  
OCD calibration default  
OCD impedance adjust  
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst  
code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS  
command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in the  
following table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is  
adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will  
be adjusted to the same driver strength setting.  
The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement  
code has no effect. The default setting maybe any step within the 16 step range. When Adjust mode command is  
issued, AL from previously set value must be applied.  
Table 10. OCD adjust mode program  
4bit burst code inputs to all DQs  
Operation  
Pull-down driver strength  
DT0  
0
DT1  
0
DT2  
0
DT3  
0
Pull-up driver strength  
NOP  
NOP  
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
1
0
Increase by 1 step  
Decrease by 1 step  
NOP  
NOP  
NOP  
Increase by 1 step  
Decrease by 1 step  
Increase by 1 step  
Increase by 1 step  
Decrease by 1 step  
Decrease by 1 step  
NOP  
Increase by 1 step  
Decrease by 1 step  
Increase by 1 step  
Decrease by 1 step  
Other Combinations  
Reserved  
Rev. 1.1  
14  
Jan. /2016