EtronTech
EM68916CWQA
z Extended Mode Register Set (EMRS )
-
EMR(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength,
ODT value selection and additive latency. The default value of the extended mode register is not defined,
therefore the extended mode register must be written after power-up for proper operation. The extended
mode register is written by asserting LOW on CS#, RAS#, CAS#, WE# and HIGH on BA0, while controlling
the states of address pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already
HIGH prior to writing into the extended mode register. The mode register set command cycle time (tMRD
)
must be satisfied to complete the write operation to the extended mode register. Mode register contents
can be changed using the same command and clock cycle requirements during normal operation as long
as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half
strength data-output driver. A3~A5 determine the additive latency, A2 and A6 are used for ODT value
selection, A7~A9 are used for OCD control, A10 is used for DQS# disable.
-
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time
the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be
issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for
synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
Table 6. Extended Mode Resistor EMR (1) Bitmap
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 Address Field
Extended Mode Register
0
1
Qoff
0
DQS# OCD program
Rtt Additive Latency Rtt D.I.C DLL
BA1 BA0 MRS mode
A6 A2
Rtt(NOMINAL)
ODT Disable
0
0
1
1
0
1
0
1
MR
0
0
1
1
0
1
0
1
A0
0
DLL Enable
Enable
Ω
75
EMR(1)
EMR(2)
EMR(3)
1
Disable
Ω
150
Ω
50
A9
0
A8
0
A7 OCD Calibration Program
Output Driver
Impedance Control
Full strength
A1
OCD Calibration mode exit; maintain setting
0
1
0
0
1
0
0
Drive(1)
0
1
Drive(0)
0
1
Reduced strength
Adjust mode*1
OCD Calibration default*2
1
0
1
1
A5 A4 A3
Additive Latency
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
A12
Qoff *3
0
0
0
1
1
1
1
1
0
1
Output buffer enabled
Output buffer disabled
2
A10
0
DQS#
3
Enable
Disable
4
1
5
Reserved
Reserved
NOTE 1: When Adjust mode is issued, AL from previously set value must be applied.
NOTE 2: After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000.
NOTE 3: Output disabled – DQs, DQSs, DQSs#.This feature is intended to be used during IDD characterization of read
current.
Etron Confidential
10
Rev. 1.1
Apr. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
