EtronTech
T0
CLK
T1
T2
COM M AND
NOP
WRITE A
WRITE B
1 Clk Interval
DQ's
DIN A0
DIN B0
4M x 32 LPSDRAM
T3
T4
T5
T6
EM669325
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0
CLK
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
don't care
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data for the write is masked.
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued
m
cycles after the clock edge in which the last data-in element
is registered, where
m
equals t
WR
/t
CK
rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0
CLK
T1
T2
T3
T4
T5
T6
DQM
tRP
COMM AND
WRITE
NOP
Precharge
NOP
NOP
Activate
NOP
ADDRESS
BA NK
COL n
DI N
n
DIN
n+1
BANK (S)
tWR
ROW
DQ
: don't care
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
Preliminary
10
Rev 0.6
Sep. 2003
ETRON [ ETRON TECHNOLOGY, INC. ]
