Et r on Tech
EM658160
4Mx16 DDR SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3 0.3 V, Ta = 0~70 °C)
- 3.3/3.5/4/5/6/7/8
Symbol
Parameter
Row cycle time
Min.
Max.
Unit
tRC
44/44/44/55/60/70/80
56/56/56/70/84/91/96
ns
ns
tRFC
tRAS
tRCD
tRP
Refresh row cycle time
Row active time
32/32/32/40/42/49/56
12/12/12/15/18/21/24
12/12/12/15/18/21/24
120000
ns
ns
ns
/RAS to /CAS Delay
Row precharge time
tRRD
twR
Row active to Row active delay
Write recovery time
6.6/7/8/10/12/14/16
2
ns
tCK
tCDLR Last data in to Read command
Col. Address to Col. Address delay
2.5tCK- DQSS
t
tCK
tCK
tCCD
tCK
1
Clock cycle time
CL*=3
CL*=2.5
CL*=2
3.3/3.5/4/5/6/7/8
5/5/5.5/6/7.5/8/9
6/6/7/8/9/10/11
0.45
15
15
ns
15
tCH
tCL
tDQSCK
tAC
Clock high level width
Clock low level width
0.55
tCK
0.45
0.55
tCK
ns
DQS-out access time from CK,/CK
Output access time from CK,/CK
-0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8 0.6/0.6/0.6/0.7/0.7/0.75/0.8
-0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8 0.6/0.6/0.6/0.7/0.7/0.75/0.8
ns
ns
tDQSQ DQS-DQ Skew
-0.5/-0.5/-0.5/-0.5/-0.5/-0.5/-0.6
0.5/0.5/0.5/0.5/0.5/0.5/0.6
tRPRE Read preamble
0.9
1.1
0.6
tCK
tCK
tCK
ns
tRPST Read postamble
0.4
tDQSS CK to valid DQS-in
tWPRES DQS-in setup time
tWPREH DQS-in hold time
0.75
1.25
0.4/0.4/0.4/0.4/0.45/0.5/0.55
0.4/0.4/0.4/0.4/0.45/0.5/0.55
ns
tWPST DQS write postamble
tDQSH DQS in high level pulse width
tDQSL DQS in low level pulse width
0.4
0.6
0.6
0.6
tCK
tCK
0.4
0.4
tCK
ns
Address and Control input setup time
Address and Control input hold time
tIS
1.1
ns
tIH
1.1
tMRD
tDS
tDH
tQH
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Output DQS valid window
1
tCK
ns
0.4/0.4/0.4/0.4/0.45/0.5/0.55
0.4/0.4/0.4/0.4/0.45/0.5/0.55
0.3
ns
tCK
ns
tPDEX Power down exit time
tIS+1tCK
tIS+2tCK
tCK
tXSA
Self refresh exit to active
command delay
12/12/11/11/10/10/10
tCK
tXSR
Self refresh exit to read
command delay
200
Etron Confidential
10
Rev. 1.1
Jan. 2002
ETRON [ ETRON TECHNOLOGY, INC. ]
