EtronTech
EM63A165
Figure 15.1. Interleaved Column Write Cycle
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBw
CBy
CBz
CBx
CAy
RAx CAx RBw
CBw
A0~A9,A11
& A12
tRP
tWR tRP
tRCD
DQM
DQ
tRRD
DAx0
Hi-Z
DBz2
DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1DBy0 DBy1 DAy0 DAy1
DBz0 DBz1
DBz3
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command Command
Bank B Bank B
Write
Write
Write
Write
Command
Bank B
Precharge
Command
Bank B
Command Command
Bank B
Bank A
Precharge
Write
Command
Bank A
Command
Bank A
51
Rev 1.1 Apr. 2007