EtronTech
EM63A165
Electrical Characteristics and Recommended A.C. Operating Conditions
±
(VDD = 3.3V 0.3V, TA = 0~70°C) (Note: 5, 6, 7, 8)
-6/7
Symbol
A.C. Parameter
Min.
Max.
Unit Note
tRC
Row cycle time
(same bank)
60/63
60/70
15/20
tRFC
tRCD
Refresh cycle time
RAS# to CAS# delay
(same bank)
tRP
Precharge to refresh/row activate command
(same bank)
15/20
tRRD
Row activate to row activate delay
(different banks)
12/14
12/14
42/45
tRSC
tRAS
Mode register set cycle time
Row activate to precharge time
(same bank)
120000
tWR
Write recovery time
12/14
-/12
ns
9
tCK2
tCK3
tCH
tCL
CL* = 2
Clock cycle time
CL* = 3
6/7
10
10
Clock high time
Clock low time
2/2.5
2/2.5
tAC2
tAC3
tOH
tLZ
CL* = 2
-/6.5
Access time from CLK
10
9
(positive edge)
CL* = 3
5/5.4
Data output hold time
Data output low impedance
Data output high impedance
2.5/2.7
0
2.5/2.7
1.8/1.8
1
tHZ
tIS
5/5.4
8
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Transition time of CLK
10
10
tIH
tT
1
10
tREF
Refresh interval time
7.8
µs
*
CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS. Overshoot VIH(Max) = VDD+2.0V for pulse width ≤ 3ns. Undershoot
VIL(Min) = -2.0V for pulse width ≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK
.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
19
Rev 1.1 Apr. 2007
ETRON [ ETRON TECHNOLOGY, INC. ]
