EM63A165
EtronTech
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
•
Table 8. Burst Definition
Start Address
Burst Length
Sequential
Interleave
A2
X
X
X
X
X
X
0
0
0
0
1
A1
X
X
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
2
4
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
n, n+1, n+2, n+3, …511, 0,
1, 2, … n-1, n, …
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
1
0
0
1
8
1
1
1
1
Full page location = 0-511
Not Support
CAS Latency Field (A6~A4)
•
This field specifies the number of clock cycles from the assertion of the Read command to the first read data.
The minimum whole value of CAS Latency depends on the frequency of CLK. The minimum whole value
satisfying the following formula must be programmed into this field.
tCAC(min) ≤ CAS Latency X tCK
Table 9. CAS Latency
A6
0
A5
0
A4
0
CAS Latency
Reserved
Reserved
2 clocks
0
0
1
0
1
0
0
1
1
3 clocks
1
X
X
Reserved
Test Mode field (A8~A7)
•
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 10. Test Mode
A8
0
A7
0
Test Mode
normal mode
0
1
Vendor Use Only
Vendor Use Only
1
X
Rev. 2.2
14
Dec. /2013
ETRON [ ETRON TECHNOLOGY, INC. ]
