EM639325
EtronTech
Table 5. Mode Register Bitmap
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
0
0
0
0
W.B.L
TM
CAS Latency
Burst Length
A9 Write Burst Length
A8
0
1
A7 Test Mode
A3 Burst Type
0
1
Burst
Single Bit
0
0
1
Normal
Reserved
Reserved
0
1
Sequential
Interleave
0
A6
0
0
A5
0
0
A4
0
1
CAS Latency
Reserved
Reserved
2 clocks
A2
0
0
A1
0
0
A0
0
1
Burst Length
1
2
4
0
1
0
0
1
0
0
1
1
3 clocks
0
1
1
8
1
0
0
Reserved
1
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
Note: Column address is repeated until terminated in Full Page Mode
Figure 16. Mode Register Set Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
tMRD
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
Hi-Z
PrechargeAll
Mode Register
Set Command
Any
Command
Don’t Care
Rev. 2.1
14
Aug. /2015
ETRON [ ETRON TECHNOLOGY, INC. ]
