EtronTech
EM639165
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued
m
cycles after the clock edge in which the last data-in element
is registered, where
m
equals t
WR
/t
CK
rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0
CLK
T1
T2
T3
T4
T5
T6
DQM
tRP
COMMAND
WRITE
NOP
Precharge
NOP
NOP
Activate
NOP
ADDRESS
BANK
COL n
DIN
n
DIN
n+ 1
BANK (S)
ROW
tWR
DQ
: don't care
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
7
Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",
A0-A8 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + t
WR
+ t
RP
(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0
CLK
Bank A
Activate
Write A
AutoPrecharge
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
DAL
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DIN A0
DIN A1
*
t
DAL
DIN A0
DIN A1
t
DAL
=
t
WR
+
t
RP
*
*
Begin AutoPrecharge
Bank can be reactivated at completion of
t
DAL
Burst Write with Auto-Precharge
(Burst Length = 2, CAS# Latency = 2, 3)
8
Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mode register. One clock cycle is required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as all banks are in the idle state.
11
Rev 1.6 Feb. 2007
ETRON [ ETRON TECHNOLOGY, INC. ]
