EM639165
POWER ON SEQUENCE
Before starting normal operation, the following power on
sequence is necessary to prevent a SDRAM from damaged
or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE
high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input con-
ditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.
5. Issue a mode register set command to initialize the mode
register.
After these sequence, the SDRAM is idle state and ready
for normal operation.
CLK
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
V
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be pro-
grammed by setting the mode register (MRS). The mode
register stores these data until the next MRS command,
which may be issued when all banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for new
command.
BA0 BA1 A1 1 A1 0 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
LTMODE
BT
BL
BL
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
CL
000
001
LATENCY
MODE
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
/CAS LATENCY
R
R
2
3
R
R
R
R
R: Reserved for Future Use
FP: Full Page
BURST
LENGTH
101
110
111
BURST
TYPE
0
1
SEQUENTIAL
INTERLEAVED
Preliminary
13
Rev 1.0
Feb. 2001
ETRON [ ETRON TECHNOLOGY, INC. ]
