EtronTech
EM638325
2Mega x 32 SDRAM
Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RBx
RAx
RBy
RBy
RAx
CBx
CAx
RBx
A0~A9
DQM
tRP
Hi-Z
DQ
Ax
Ax+2Ax-2
Ax-1 Ax
Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4Bx+5
Full Page burst operation does not
Ax+1
Bx+6
Activate
Read
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Command Command
terminate when the burst length is satisfied;
Bank A
Bank A
The burst counter wraps
from the highest order
page address back to zero
during this time interval
the burst counter increments and continues
bursting beginning with the starting address.
Burst Stop
Command
Preliminary
60
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
