EtronTech
EM638325
2Mega x 32 SDRAM
Figure 12.3. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RAy
RAy
CAy
RAx
CAx
CBx
RBx
A0~A9
DQM
tRCD
tWR*
tRP
tWR*
Hi-Z
DQ
DAy0 DAy1 DAy2
DBx5 DBx6
DAx7 DBx0 DBx1DBx2 DBx3 DBx4
DBx7
DAy3
DAx0DAx1
DAx6
DAx2 DAx3DAx4 DAx5
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank B
*
tWR > tWR(min.)
Preliminary
43
Rev 1.4
Oct. 2005