EtronTech
T0
CLK
tCK2
CKE
T1
T2
T3
T4
2Mega x 32 SDRAM
T5
T6
T7
T8
T9
EM638325
T10
Clock min.
CS#
RAS#
CAS#
WE#
Address Key
ADDR.
DQM
t
RP
DQ
Hi-Z
PrechargeAll
Mode Register
Set Command
Any
Command
Mode Register Set Cycle (CAS# Latency = 2, 3)
The mode register is divided into various fields depending on functionality.
Address BS0,1 A10/AP
Function RFU*
RFU*
A9
WBL
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Test Mode
CAS Latency
Burst Length
*Note: RFU (Reserved for future use) should stay
“0”
during MRS cycle.
•
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst
Length to be 2, 4, 8, or full page.
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Burst Length
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Preliminary
12
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
