EtronTech
EM638165
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A
DOUT A
DOUT A
DOUT A
3
CAS# latency=2
0
1
2
t
, DQ's
CK2
DOUT A
DOUT A
DOUT A
DOUT A
3
CAS# latency=3
, DQ's
0
1
2
t
CK3
Burst Read Operation
(Burst Length = 4, CAS# Latency = 2, 3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write command to the same bank or the other active
bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
3
0
0
1
2
t
, DQ's
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
3
0
0
1
2
t
CK3
Read Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following three figures). If the data output of the burst read occurs at
the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to
the Write command to avoid internal bus contention.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
DQ's
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
DINB
NOP
NOP
DOUT A
0
DINB
DINB
2
0
1
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval
(Burst Length 4, CAS# Latency = 3)
Preliminary
Rev 0.6
Feb. 2001
7