EM638165
EtronTech
Table 5. Mode Register Bitmap
BA1 BA0 A11 A10
RFU* RFU*
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
0
WBL Test Mode
CAS Latency
Burst Length
A9 Write Burst Length
A8 A7
Test Mode
Normal
Vendor Use Only
Vendor Use Only
A3
0
1
Burst Type
Sequential
Interleave
0
1
Burst
Single Bit
0
1
0
0
0
1
A6
0
0
0
0
A5
0
0
1
1
A4
0
1
0
1
CAS Latency
Reserved
Reserved
2 clocks
3 clocks
Reserved
A2
0
0
0
0
A1
0
0
1
1
A0
Burst Length
0
1
0
1
1
1
2
4
8
1
0
0
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
tMRD
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
Hi-Z
PrechargeAll
Mode Register
Set Command
Any
Command
Don’t Care
Figure 16. Mode Register Set Cycle
Rev. 5.2
12
Rev. 5.2
Dec. /2013
ETRON [ ETRON TECHNOLOGY, INC. ]
