EtronTech
EM636327
Figure 15.1. Interleaved Column Write Cycle
(Burst Length=4, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CA S#
WE#
DSF
BS
A 9
RAx
RBw
CBy
CBz
RAx CAx RBw
CBw
CBx
CAy
A0~A8
DQM
DQ
RP
t
tRCD
tRRD
tWR tRP
Hi-Z
DAx0
DBz2
DBz3
DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1
DBz0 DBz1
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command Command
Bank B Bank B
Write
Write
Write
Precharge
Command
Bank B
Command Command
Bank B
Bank A
Write
Command
Bank A
Preliminary
1998
December
54