EtronTech
Pin Descriptions
Table 1 shows the details for pin number, symbol, type, and description.
Table 1. Pin Details of EM636327
Pin Number Symbol Type Description
55
CLK
EM636327
Input
Clock:
CLK is driven by the system clock. All SGRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
Input
Clock Enable:
CKE activates(HIGH) and deactivates(LOW) the CLK signal.
If CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the
state of output and burst address is frozen as long as the CKE remains low.
When both banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes. CKE is synchronous
except after the device enters Power Down and Self Refresh modes, where
CKE becomes asynchronous until exiting the same mode. The input buffers,
including CLK, are disabled during Power Down and Self Refresh modes,
providing low standby power.
Input
Bank Select:
BS defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. BS is also used to program the
10th bit of the Mode and Special Mode registers.
Input
Address Inputs:
A0-A9 are sampled during the BankActivate command (row
address A0-A9) and Read/Write command (column address A0-A7 with A9
defining Auto Precharge) to select one location out of the 256K available in
the respective bank. During a Precharge command, A9 is sampled to
determine if both banks are to be precharged (A9 = HIGH). The address
inputs also provide the op-code during a Mode Register Set or Special Mode
Register Set command.
Input
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
Input
Row Address Strobe:
The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive
edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is
asserted "HIGH," either the BankActivate command or the Precharge
command is selected by the WE# signal. When the WE# is asserted "HIGH,"
the BankActivate command is selected and the bank designated by BS is
turned on to the active state. When the WE# is asserted "LOW," the
Precharge command is selected and the bank designated by BS is switched
to the idle state after the precharge operation.
Input
Column Address Strobe:
The CAS# signal defines the operation commands
in conjunction with the RAS# and WE# signals and is latched at the positive
edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the
column access is started by asserting CAS# "LOW." Then, the Read or Write
command is selected by asserting WE# "LOW" or "HIGH."
Input
Write Enable:
The WE# signal defines the operation commands in
conjunction with the RAS# and CAS# signals and is latched at the positive
edges of CLK. The WE# input is used to select the BankActivate or
Precharge command and Read or Write command.
54
CKE
29
BS
31-34,
47-50,
30, 51
A0-A9
28
CS#
27
RAS#
26
CAS#
25
WE#
Preliminary
3
December
1998
ETRON [ ETRON TECHNOLOGY, INC. ]
