EtronTech
T0
CLK
T1
T2
T3
T4
T5
T6
EM636327
T7
T8
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
COM MAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
don't care
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data for the write is masked.
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued
m
cycles after the clock edge in which the last data-in element
is registered, where
m
equals t
WR
/t
CK
rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0
CLK
T1
T2
T3
T4
T5
T6
DQM
tRP
COM MAND
WRITE
NOP
Precharge
NOP
NOP
Activate
NOP
ADDRESS
BA N K
COL n
DIN
n
DIN
n+ 1
BANK (S)
tWR
ROW
DQ
: don't care
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
When the Burst-Read-Single-Write mode is selected, the write burst length is 1 regardless of
the read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8
Block Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "H", BS = Bank, A9 = "L", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A
single data value, which was previously loaded in the Color register, is written to the block of eight
consecutive column locations addressed by inputs A3~A7. The information on the DQs which are
Preliminary
11
December
1998
ETRON [ ETRON TECHNOLOGY, INC. ]
