EtronTech
EM636165
1M x 16 SDRAM
Figure 15.1. Interleaved Column Write Cycle
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBw
CBy
CBz
RAx CAx RBw
CBw
CBx
CAy
A0~A9
tRP
tWR tRP
tRCD
tRRD
DQM
DQ
Hi-Z
DAx0
DBz2
DBz3
DAx1 DAx2 DAx3 DBw0DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1
DBz0 DBz1
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command Command
Bank B Bank B
Write
Write
Command Command
Bank B Bank A
Write
Write
Command
Bank B
Precharge
Command
Bank B
Precharge
Write
Command
Bank A
Command
Bank A
Preliminary
52
Rev. 2.7 Mar. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
