EtronTech
EM636165
1M x 16 SDRAM
Figure 18.3. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBy
RBy
RBx
RBx
CAx
RAx
CBx
A0~A9
DQM
tRP
Hi-Z
Ax+1
DQ
Ax
Ax+2 Ax-2 Ax-1 Ax
Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Precharge
Command
Bank B
Activate
Command
Bank B
Full Page burst operation does not
Command
Bank B
terminate when the burst length is
satisfied; the burst counter
increments and continues
The burst counter wraps
from the highest order
page address back to zero
during this timeinterval
bursting beginning with the
starting address.
Burst Stop
Command
Preliminary
63
Rev. 2.7 Mar. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
