EtronTech
EM636165-XXI
1M x 16 SDRAM
Figure 5. Self Refresh Entry & Exit Cycle
T0
T1
T2
T3
T4
T5
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
T6
CLK
*Note 2
tRC(min) *Note 7
*Note 4
*Note 1
*Note 3
CKE
CS#
tPDE
tSRX
*Note 5
*Note 6
tIS
RAS#
CAS#
A11
*Note 8
*Note 8
A0-A9
WE#
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Enter
SelfRefreshExit
AutoRefresh
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
1. System clock restart and be stable before returning CKE high.
2. Enable CKE and CKE should be set high for minimum time of tSRX
.
3. CS# starts from high.
4. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Preliminary
25
Rev. 1.1 Apr. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
