EtronTech
EM636165-XXI
1M x 16 SDRAM
Figure 12.3. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAy
RAy
RAx
RAx
RBx
RBx
CAy
CAx
CBx
A0~A9
DQM
tRCD
tWR*
tRP
tWR*
Hi-Z
DBx7
DAy3
DAy0 DAy1 DAy2
DBx5 DBx6
DAx6
DAx7 DBx0 DBx1 DBx2 DBx3 DBx4
DQ
DAx2 DAx3 DAx4 DAx5
DAx0 DAx1
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
*
tWR > tWR(min.)
Preliminary
44
Rev. 1.1 Apr. 2005