EtronTech
AC Test Condition
•
Output load : 30pF + one TTL gate
•
Input pulse level : 0.4V, 2.4
•
Timing measurements : 0.5 x VCC
•
tR, tF : 5ns
EM567169BC
AC Test Loads
R
L
= 50
Ω
D
OUT
Z
0
= 50
Ω
Note:
1. Including scope and jig capacitance
C
L
= 30 pF
1
V
L
= 1.5 V
State Diagram
Deep Power Down Exit
Sequence
Deep Power Down Entry
Sequence
CE1# = VIH or VIL,
CE2=VIH
Deep Power
Down Mode
CE2=VIH
CE2=VIL
Power
on
Initial State
(Wait 200µs)
Active
CE1# =VIL,
CE2=VIH,
CE2=VIL
Power Up Sequence
CE2=VIH,
CE1# =VIH
or UB#, LB#
=VIH
Standby
Standby Mode Characteristics
Power Mode
Standby
Deep Power Down
Memory Cell Data
Valid
Invalid
Standby Current (µA)
100
10
Wait Time
0 ns
200 µs
7
Rev 0.6
Apr. 2004