Et r on Tech
EM566169BC
Avoid Timing
Etron Pseudo SRAM has a timing which is not supported at read operation. If your system has multiple
invalid address signal shorter than tRC during over 15µs at read operation shown as in Abnormal Timing, it
requires a normal read timing at leat during 15 µs shown as in Avoidable timing 1 or toggle CE1# to high (
tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
15µs
CE1#
WE#
< tRC
Address
Avoidable Timing 1
15µs
CE1#
WE#
tRC
Address
Avoidable Timing 2
15µs
CE1#
tRC
WE#
< tRC
Address
14
Rev 0.6
Apr. 2004
ETRON [ ETRON TECHNOLOGY, INC. ]
