Et r on Tech
EM565161
Write Cycle4
(UB#, LB# Controlled)(See Note 4)
t
W C
A d d r e s s
t
t
t
A S
W P
W R
W E #
C E 1 #
C E 2
t
C W
t
t
C W
B W
U B #
L B #
,
t
t
W H Z
B L Z
D
O U T
t
L Z
t
t
D S
D H
D
(S e e N o te 5 )
V A L I D D A T A IN
I N
Note:
1. WE# remains HIGH for the read cycle.
2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high
impedance.
3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at
high impedance.
4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
Preliminary
10
Rev 0.9
Jan 2002
ETRON [ ETRON TECHNOLOGY, INC. ]
