24C02 / 24C04 / 24C08 / 24C16
Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA_IN
tAA
tDH
tBUF
SDA_OUT
Write Cycle Timing
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
SCL
8th BIT
ACK
SDA
(1)
tWR
STOP
START
CONDITION
CONDITION
Note
1. The write cycle time tWR is the time from a valid stop condition
of a write sequence to the end of the internal clear/write cycle.
BEIJING ESTEK ELECTRONICS CO.,LTD
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