ES6218A PRODUCT BRIEF
ES6218A PIN DESCRIPTION
Table 1 ES6218A Pin Description (Continued)
Name
DCLK
UDAC
Pin Numbers
105
I/O
I
O
Definition
Clock input to PLL.
Video DAC output.
Value
0
1
2
3
4
5
6
7
106
8
9
10
11
12
13
14
Y DAC
C DAC
U DAC
(pin 113) (pin 108) (pin 106)
Y
Y
Y
N/A
N/A
Y
Y
G
Y
G
G
G
Y
Y
G
C
C
C
N/A
N/A
Pb
Pb
B
Pb
B
R
R
Pr
Pr
R
N/A
CVBS2
N/A
CVBS2
N/A
Pr
Pr
R
Pr
R
B
B
Pb
Pb
B
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
YUV0
PIXOUT0
YUV1
VREF
PIXOUT1
YUV2
CDAC
PIXOUT2
YUV3
COMP
PIXOUT3
YUV4
RSET
PIXOUT4
110
109
108
107
O
O
O
I
O
O
O
O
O
I
O
O
I
O
YUV pixel 0 output data.
CCIR656 output pixel 0.
YUV pixel 1 output data.
Internal voltage reference to video DAC. Bypass to ground with 0.1-µF capacitor.
CCIR656 output pixel 1.
YUV pixel 2 output data.
Video DAC output. Refer to description and matrix for UDAC pin 106.
CCIR656 output pixel 2.
YUV pixel 3 output data.
Compensation input. Bypass to ADVEE with 0.1-µF capacitor.
CCIR656 output pixel 3.
YUV pixel 4 output data.
DAC current adjustment resistor input.
CCIR656 output pixel 4.
ESS Technology, Inc.
SAM0575-021805
5
ESS [ ESS Technology,Inc ]
