ES6218A PRODUCT BRIEF
ES6218A PIN DESCRIPTION
Table 1 ES6218A Pin Description (Continued)
Name
TSD0
33
SEL_PLL0
TSD1
36
SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SPDIF_OUT
37
38
39
40
I
O
O
I/O
I/O
O
I
41
SEL_PLL3
Refer to the description and matrix for SEL_PLL2 pin 32.
Audio transmit serial data output 2. This pin must be pulled down to VSS via a
4.7-kΩ resistor for proper operation.
Audio transmit serial data output 3.
Audio master clock for audio DAC.
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
S/PDIF output.
Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only
during reset.
SEL_PLL3
0
1
SPDIF_IN
RSD
RWS
RBCK
CAMIN3
48
PIXIN3
XIN
XOUT
AVEE
AVSS
DMA[11:0]
DCAS#
DOE#
70
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
DB[15:0]
DCS[1:0]#
DQM
DSCK
71
72
73
74
77-82, 85-90, 93-96
97,100
101
102
O
O
O
O
O
I/O
O
O
O
DRAM clock enable.
DRAM write enable.
DRAM row address strobe.
DRAM bank select 0.
DRAM bank select 1.
DRAM data bus.
DRAM chip select.
Data input/output mask.
Output clock to DRAM.
49
50
51
52
53-58, 61-66
69
I
I
O
P
G
O
O
O
CCIR656 input pixel 3.
27-MHz crystal input.
27-MHz crystal output.
Analog power for PLL.
Analog ground for PLL.
DRAM address bus.
DRAM column address strobe.
DRAM output enable.
42
45
46
47
I
I
I
I
I
S/PDIF input.
Audio receive serial data.
Audio receive frame sync.
Audio receive bit clock.
Camera YUV 3.
Clock Source
Crystal oscillator
DCLK input
I
O
Refer to the description and matrix for SEL_PLL2 pin 32.
Audio transmit serial data output 1.
Pin Numbers
I/O
O
Definition
Audio transmit serial data output 0.
4
SAM0575-021805
ESS Technology, Inc.
ESS [ ESS Technology,Inc ]
