ES6178 PRODUCT BRIEF
ES6178 PIN DESCRIPTION
Table 1
Name
TSD1
36
SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SEL_PLL3
37
38
39
40
I
O
O
I/O
I/O
I
Refer to the description and matrix for SEL_PLL2 pin 32.
Audio transmit serial data output 2. This pin must be pulled down to VSS via a
4.7-kΩ resistor for proper operation.
Audio transmit serial data output 3.
Audio master clock for audio DAC.
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only
during reset.
SEL_PLL3
41
0
1
SPDIF_OUT
SPDIF_IN
RSD
RWS
RBCK
CAMIN3
48
PIXIN3
XIN
XOUT
AVEE
AVSS
DMA[11:0]
DCAS#
DOE#
70
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
DB[15:0]
DCS[1:0]#
DQM
DSCK
DCLK
4
71
72
73
74
77-82, 85-90, 93-96
97,100
101
102
105
SAM0527-052705
O
O
O
O
O
I/O
O
O
O
I
DRAM clock enable.
DRAM write enable.
DRAM row address strobe.
DRAM bank select 0.
DRAM bank select 1.
DRAM data bus.
DRAM chip select.
Data input/output mask.
Output clock to DRAM.
Clock input to PLL; (5V tolerant input).
ESS Technology, Inc.
49
50
51
52
53-58, 61-66
69
I
I
O
P
G
O
O
O
CCIR656 input pixel 3.
27-MHz crystal input.
27-MHz crystal output.
Analog power for PLL.
Analog ground for PLL.
DRAM address bus.
DRAM column address strobe.
DRAM output enable.
42
45
46
47
O
I
I
I
I
I
S/PDIF output.
S/PDIF input; (5V tolerant input).
Audio receive serial data; (5V tolerant input).
Audio receive frame sync; (5V tolerant input).
Audio receive bit clock; (5V tolerant input).
Camera YUV 3.
Clock Source
Crystal oscillator
DCLK input
ES6178 Pin Description (Continued)
Pin Numbers
I/O
O
Definition
Audio transmit serial data output 1.
ESS [ ESS Technology,Inc ]
