ES4318 PRODUCT BRIEF
Name
TDMDX
RSEL
Number
I/O
O
I
Definition
TDM transmit data.
ROM Select
RSEL
0
1
Selection
16-bit ROM
8-bit ROM
25
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
SEL_PLL1
TSD
SEL_PLL0
28
29
30
31
32
I
I
I
O
O
I
O
I
TDM receive data.
TDM clock input.
TDM frame synch.
TDM output enable, active low.
Audio transmit frame sync.
Select PLL1.
Audio transmit serial data port.
Select PLL0.
SEL_PLL2
0
0
1
1
SEL_PLL0
0
1
0
1
Clock Output
2.5 x DCLK
3 x DCLK
3.5 x DCLK
4 x DCLK
33
SEL_PLL2
MCLK
TBCK
SPDIF_DOBM
RSD
RWS
RBCK
APLLCAP
XIN
XOUT
DMA[11:0]
DCAS#
DOE#
DSCK_EN
DWE#
DRAS[2:0]#
DB[15:0]
DCS[1:0]#
DQM
DSCK
DCLK
YUV[7:0]
PCLK2XSCN
PCLKQSCN
VSYNCH#
HSYNCH#
HD[15:0]
HCS1FX#
HCS3FX#
HIOCS16#
HA[2:0]
VPP
HWR#/DCI_ACK#
HRD#/DCI_CLK
HD[15:0]
HWRQ#
HRDQ#
HIRQ
HRST#
HIORDY
HWR#
AUX[7:0]
LOE#
LCS[3:0]#
LD[15:0]
LWRLL#
LWRHL#
NC
36
39
40
41
45
46
47
48
49
50
66:61,58:53
69
70
71
74:72
96:93,90:85,82:77
97,100
101
102
105
115:113,110:106
116
117
118
119
141:140,137:131,128:122
152
153
151
158, 155:154
159
149
150
141:140,137:131,128:122
142
143
144
145
146
149
169:165,162:160
170
176:173
197:194, 191:185, 182:178
198
199
37,38,42,203:202
I/O
I/O
O
I
I
I
I
I
O
O
O
O
I
O
O
I/O
O
O
O
I
O
I/O
I/O
I/O
I/O
O
O
O
I
I/O
I
I,I
I,I
I/O
O
O
I/O
O
I
O
I/O
O
O
I/O
O
O
Select PLL2. See the table for pin number 33.
Audio master clock for audio DAC.
Audio transmit bit clock.
S/PDIF (IEC958) Format Output.
Audio receive serial data.
Audio receive frame synch.
Audio receive bit clock.
Analog PLL Capacitor.
Crystal input.
Crystal output.
DRAM address bus.
Column address strobe, active low.
Output enable, active low.
Clock Enable, active low.
DRAM write enable, active low.
Row address strobe, active low.
DRAM data bus.
SDRAM chip select [1:0], active low.
Data input/output mask.
Clock to SDRAM.
Clock Input (27 MHz)
8-bit YUV output.
2X pixel clock.
Pixel clock.
Vertical sync for screen video interface, programmable for rising or falling edge, active low.
Horizontal sync for screen video interface, programmable for rising or falling edge, active low.
Host data bus
Host select 1.
Host select 3.
Device 16-bit data transfer.
Host address bus.
Peripheral protection voltage.
Host write/DCI Interface Acknowledge Signal, active low.
Host read/DCI Interface Clock.
Host data bus.
Host write request.
Host read request.
Host interrupt.
Host reset.
Host I/O ready.
Host write request.
Auxiliary ports.
Device output enable, active low.
Chip select [3:0], active low.
Device data bus.
Device write enable, active low.
Device write enable, active low.
No connect.
ESS Technology, Inc.
SAM0377-052101
3
ESS [ ESS Technology,Inc ]
