ES3883 PRODUCT BRIEF
Table 1 Visba ES3883 Pin Description (Continued)
Name
AUX14
AUX15
DSC_D[7:0]
DSC_S
DCLK
EXT_CLK
RESET_B
MUTE
MCLK
TWS
SPLL_OUT
TSD
TBCK
RWS
SEL_PLL1
Number
39
40
81,83,85,93,95,97,99,8
10
12
13
15
17
19
21
22
I/O Definition
I/O
I/O
I/O
I
O
I
I
O
I
I
O
I
I
O
I
Servo SCOR (S0S1), interrupt input, or general-purpose I/O
Interrupt input or general-purpose I/O
Data for programming to access internal registers
Strobe for programming to access internal registers
Dual-purpose. DCLK is the MPEG decoder clock
EXT_CLK is the external clock. EXT_CLK is an input during bypass PLL mode
Video reset (active-low)
Audio mute
Audio master clock.
Dual-purpose. TWS is the transmit audio frame sync
SPLL_OUT is the select PLL output
Transmit audio data input
Transmit audio bit clock
Dual-purpose. RWS is the receive audio frame sync
SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
SEL_PLL1
0
0
1
1
SEL_PLL0
0
1
0
1
DCLK
Bypass PLL (input mode)
27 MHz (output mode)
32.4 MHz (output mode)
40.5 MHz (output mode)
23
RSTOUT_B
NC
RSD
SEL_PLL0
RBCK
SER_IN
VSSAA
VCM
VREFP
VCCAA
AOR+, AOR–
AOL–, AOL+
MIC1
MIC2
VREF
VREFM
RSET
COMP
VSSAV
CDAC
VCCAV
YDAC
VDAC
ACAP
XOUT
XIN
PCLK
2XPCLK
HSYN_B
VSYN_B
YUV[7:0]
24
2:4,27:30,76
33
O
O
I
O
I
37
41,51
42
43
44
45:46
47:48
49
50
52
53
54
55
56:57,62:63
58
59,60
61
64
65
71
74
79
80
82
84
86:89,92,94,96,98
I
I
I
I
O
O
I
I
I
I
I
I
I
O
I
O
O
I
O
I
I/O
I/O
O
O
I
Reset output (active-low)
No connect.
Dual-purpose. RSD is the receive audio data input
SEL_PLL0 and SEL_PLL1 select the PLL clock frequency for the DCLK output. Refer to
the table in the definition for pin 23.
Dual-purpose. RBCK is the receive audio bit clock.
SER_IN is the serial input DSC mode:
0 = Parallel DSC mode
1 = Serial DSC mode
Audio analog ground
ADC common mode reference (CMR) buffer output. CMR is approximately 2.25V. Bypass
to analog ground with 47-µF electrolytic in parallel with 0.1
µF.
DAC and ADC maximum reference. Bypass to video CMR (VCMR) with 10
µF
in parallel with
0.1
µF.
Analog VCC, 5V
Right channel output
Left channel output
Microphone input 1
Microphone input 2
Internal resistor divider generates CMR voltage. Bypass to analog ground with 0.1
µF.
DAC and ADC minimum reference. Bypass to VCMR with 10
µF
in parallel with 0.1
µF.
Full-scale DAC current adjustment
Compensation pin
Video analog ground
Modulated chrominance output
Video VCC, 5V
Y luminance data bus for screen video port
Composite video output.
Audio CAP
Crystal output
27-MHz crystal input
13.5-MHz pixel clock.
27-MHz (2 times pixel clock)
Horizontal sync (active-low)
Vertical sync (active-low)
YUV data bus for screen video port
ESS Technology, Inc.
SAM0416-073001
3
ESS [ ESS Technology,Inc ]
