ESMT
M52D16161A
Clock Suspension & DQM Operation Cycle @ CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
C S
RA S
CA S
A D D R
BA
R a
C a
C b
C c
R a
A10 /AP
D Q
Qb0
Qa0
Qa1
Qa2
Qa3
tS H Z
Dc 2
Qb1
tS H Z
Dc 0
W E
* N o t e 1
D Q M
Cl oc k
Suspension
W r i t e
D Q M
Row A c t i ve
Read
Read
W r i t e
D Q M
Cl oc k
Suspension
Read D Q M
W r i t e
:D on' t C ar e
*Note: 1. DQM is needed to prevent bus contention.
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2009
Revision : 1.7 20/32