ESMT
M52D128168A
Operation Temperature Condition -40°C~85°C
Current
State
BA
ADDR
ACTION
NOP Æ Idle after tRP
NOP Æ Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after tRP
ILLEGAL
NOP Æ Row Active after tRCD
NOP Æ Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after tRFC
NOP Æ Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
Note
CS RAS CAS
WE
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
CA
RA
A10/AP
Precharging
2
2
2
4
L
L
X
X
X
X
X
H
H
H
L
L
L
X
H
H
L
Row
Activating
2
2
2
2
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
Refreshing
L
X
H
H
H
L
NOP Æ Idle after 2clocks
NOP Æ Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
Accessing
X
X
X
X
X
X
X
Abbreviations :
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008
Revision: 1.0 27/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
