ESMT
M52D16161A (2J)
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn
DQM BA A10/AP A9~A0 Note
CS RAS CAS WE
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
Register
Refresh
Extended Mode Register
Set
Auto Refresh
H
X
L
L
L
L
X
OP CODE
1,2
H
L
3
3
H
L
L
L
H
X
X
Entry
Self Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
3
Exit
L
H
X
X
X
X
Bank Active & Row Addr.
H
V
V
Row Address
Column
Address
Auto Precharge Disable
L
4
Read &
Column Address
H
H
X
X
L
L
H
H
L
L
H
L
X
X
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
H
L
4,5
4
(A0~A7)
Column
Address
(A0~A7)
Write & Column
Address
V
H
4,5
Burst Stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
6
4
4
Bank Selection
Both Banks
V
X
L
H
X
H
L
X
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
X
V
X
DQM
H
H
H
H
L
X
X
X
7
H
L
L
X
H
H
X
X
H
H
X
X
H
L
No Operation Command
X
Entry
Exit
L
H
X
X
Deep Power Down Mode
X
X
X
(V= Valid, X= Don’t Care, H= Logic High, L = Logic Low)
Note:
1. OP Code: Operation Code
A0~ A10/AP, BA: Program keys.(@MRS). BA=0 for MRS and BA=1 for EMRS.
2. MRS/EMRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks precharge state.
4. BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2010
Revision : 1.5 10/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
