ESMT
M52D128168A (2E)
(b) CL = 3 , B L= 4
CLK
R D
W R
D0
i ) C M D
D Q M
D Q
D2
D3
D1
W R
i i ) C M D
R D
R D
R D
R D
D Q M
D Q
D0
D2
D3
D1
i i i ) C M D
W R
D Q M
D Q
D0
D2
D3
D1
i v ) C M D
W R
D Q M
D Q
H i - Z
D2
D3
D0
D1
v ) C M D
W R
D Q M
D Q
H i - Z
Q0
D0
D2
D3
D1
* N o t e 1
*Note: 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
C L K
* N o t e 3
C M D
W R
D 0
P R E
* N o t e 2
D Q M
D Q
D 3
D 2
D 1
M a s k e d b y D Q M
*Note: 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of four banks operation.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0 21/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
