M24L816512SA-55TIG 参数 Datasheet PDF下载

ESMT

Switching Waveforms (continued)

Write Cycle 1 (

WE

Controlled)

[12, 13, 17, 18, 19]

M24L816512SA

Write Cycle 2 ( CE Controlled) [12, 13, 17, 18, 19]

Notes:

17.Data I/O is high impedance if OE

≥

V

IH

.

18.If Chip Enable goes INACTIVE simultaneously with

WE

= HIGH, the output remains in a high-impedance state.

19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc.

Publication Date

:

Jun. 2009

Revision

:

1.5

7/14