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M24L48512SA-70BEG 参数 Datasheet PDF下载

M24L48512SA-70BEG图片预览
型号: M24L48512SA-70BEG
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K ×8 )伪静态RAM [4-Mbit (512K x 8) Pseudo Static RAM]
分类和应用:
文件页数/大小: 12 页 / 274 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M24L48512SA  
Switching Characteristics (Over the Operating Range)[8] (continued)  
–55  
–60  
–70  
Parameter  
Description  
Unit  
Min.  
0
Max.  
Min.  
0
Max.  
Min.  
0
Max.  
tSA  
Address Set-up to Write Start  
ns  
ns  
tPWE  
40  
40  
45  
WE Pulse Width  
tSD  
Data Set-up to Write End  
Data Hold from Write End  
25  
0
25  
0
25  
0
ns  
ns  
ns  
tHD  
tHZWE  
25  
25  
25  
WE LOW to High Z[9, 10]  
WE HIGH to Low Z[9, 10]  
tLZWE  
5
5
5
ns  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled) [12, 13, 14]  
Read Cycle 2 (OE Controlled) [12, 14]  
Notes:  
13.Device is continuously selected. OE , CE = VIL.  
14. WE is HIGH for Read Cycle.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jul. 2008  
Revision: 1.1 5/12